library IEEE;
use IEEE.std_logic_1164.all;

entity V2to4dec is
    port (
        G: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (1 downto 0);
        Y: out STD_LOGIC_VECTOR (0 to 3)
    );
end V2to4dec;

architecture V2to4dec_a of V2to4dec is
  signal Y_s: STD_LOGIC_VECTOR (0 to 3);  -- internal signal
begin
    with A select Y_s <=
      "1000" when "00",
      "0100" when "01",
      "0010" when "10",
      "0001" when "11",
      "0000" when others;
    Y <= Y_s when G='1' else "0000";
end V2to4dec_a;