library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
    port (
        G1: in STD_LOGIC;
        G2A_L: in STD_LOGIC;
        G2B_L: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (2 downto 0);
        Y_L: out STD_LOGIC_VECTOR (0 to 7)
    );
end V74x138;

architecture V74x138_p of V74x138 is
  signal G2A, G2B: STD_LOGIC;             -- active-high version of inputs
  signal Y: STD_LOGIC_VECTOR (0 to 7);    -- active-high version of outputs
begin
  process (G1, G2A_L, G2B_L, A, G2A, G2B, Y)
    begin
    G2A <= not G2A_L; -- convert inputs
    G2B <= not G2B_L; -- convert inputs
    if (G1 and G2A and G2B)='0' then Y <= "00000000";
    else case A is 
           when "000" => Y <= "10000000";
           when "001" => Y <= "01000000";
           when "010" => Y <= "00100000";
           when "011" => Y <= "00010000";
           when "100" => Y <= "00001000";
           when "101" => Y <= "00000100";
           when "110" => Y <= "00000010";
           when "111" => Y <= "00000001";
           when others => Y <= "00000000";
         end case;
    end if;
    Y_L <= not Y;     -- convert outputs
  end process;
end V74x138_p;