library IEEE;
use IEEE.std_logic_1164.all;

entity V74x139 is
    port (
        G_L: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (1 downto 0);
        Y_L: out STD_LOGIC_VECTOR (0 to 3)
    );
end V74x139;

architecture V74x139_a of V74x139 is
  signal Y_L_i: STD_LOGIC_VECTOR (0 to 3);  -- internal signal
begin
    with A select Y_L_i <=
      "0111" when "00",
      "1011" when "01",
      "1101" when "10",
      "1110" when "11",
      "1111" when others;
    Y_L <= Y_L_i when G_L='0' else "1111";
end V74x139_a;

architecture V74x139_b of V74x139 is
  signal G: STD_LOGIC;                    -- active-high version of input
  signal Y: STD_LOGIC_VECTOR (0 to 3);    -- active-high version of outputs
  signal Yi: STD_LOGIC_VECTOR (0 to 3);   -- internal signal
begin
    G <= G_L;     -- convert input
    with A select Yi <=
      "1000" when "00",
      "0100" when "01",
      "0010" when "10",
      "0001" when "11",
      "0000" when others;
    Y   <= not Yi when G='1' else "0000";
    Y_L <= Y;     -- convert outputs
end V74x139_b;

architecture V74x139_c of V74x139 is
  signal G: STD_LOGIC;                    -- active-high version of input
  signal Y: STD_LOGIC_VECTOR (0 to 3);    -- active-high version of outputs
  component V2to4dec port (G: in STD_LOGIC;
                           A: in STD_LOGIC_VECTOR (1 downto 0);
                           Y: out STD_LOGIC_VECTOR (0 to 3) ); end component;
begin
  G <= not G_L;    -- convert input
  Y_L <= not Y;  -- convert outputs
  U1: V2to4dec port map (G, A, Y);
end V74x139_c;