library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity V74x148 is
    port (
        EI: in STD_LOGIC;
        I: in STD_LOGIC_VECTOR (7 downto 0);
        A: out STD_LOGIC_VECTOR (2 downto 0);
        EO, GS: out STD_LOGIC
    );
end V74x148;

architecture V74x148h of V74x148 is
begin
  process (EI, I)
  variable j: INTEGER range 7 downto 0;
  variable done: bit;
  begin
    EO <= '1'; GS <= '0'; done := '0'; A <= "000";
    if (EI)='0' then EO <= '0';
    else for j in 7 downto 0 loop
        if done = '1' then null;
        elsif I(j)='1' then
          GS <= '1'; done := '1'; EO <= '0'; A <= CONV_STD_LOGIC_VECTOR(j,4)(2 downto 0); 
        end if;
      end loop;   
    end if;
  end process;
end V74x148h;