library IEEE;
use IEEE.std_logic_1164.all;

entity V74x148 is
    port (
        EI_L: in STD_LOGIC;
        I_L: in STD_LOGIC_VECTOR (7 downto 0);
        A_L: out STD_LOGIC_VECTOR (2 downto 0);
        EO_L, GS_L: out STD_LOGIC
    );
end V74x148;

architecture V74x148p of V74x148 is
  signal EI, EO, GS: STD_LOGIC;            -- active-high version of inputs and outputs
  signal I: STD_LOGIC_VECTOR (7 downto 0); -- active-high version of inputs
  signal A: STD_LOGIC_VECTOR (2 downto 0); -- active-high version of outputs
-- convert an integer to an STD_LOGIC_VECTOR
    function CONV(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
    variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
    variable temp: integer;
    begin
    temp := ARG;
    for i in 0 to SIZE-1 loop
        if (temp mod 2) = 1 then result(i) := '1';
        else result(i) := '0';
        end if;
        temp := temp / 2;
    end loop;
    return result;
    end;
begin
  process (EI_L, I_L, EI, EO, GS, I, A)
  variable j: INTEGER range 7 downto 0;
  begin
    EI <= not EI_L; -- convert input
    I <= not I_L;   -- convert inputs
    EO <= '1'; GS <= '0'; A <= "000";
    if (EI)='0' then EO <= '0';
    else for j in 7 downto 0 loop
        if GS = '1' then null;
        elsif I(j)='1' then GS <= '1'; EO <= '0'; A <= CONV(j,3); 
        end if;
      end loop;   
    end if;
    EO_L <= not EO; -- convert output
    GS_L <= not GS; -- convert output
    A_L <= not A;   -- convert outputs
  end process;
end V74x148p;