-- ACTIVE-CAD-2-VHDL, 2.5.5.50, Tue Dec 15 21:54:47 1998

library IEEE;
use IEEE.std_logic_1164.all;

entity CHAPTER5 is port (
	YB_L : out STD_LOGIC_VECTOR (0 to 7);
	A : in STD_LOGIC_VECTOR (8 downto 0);
	YC_L : out STD_LOGIC_VECTOR (0 to 7);
	YA_L : out STD_LOGIC_VECTOR (0 to 7);
	YQ_L : out STD_LOGIC_VECTOR (0 to 7);
	YP_L : out STD_LOGIC_VECTOR (0 to 7);
	IN_KEYWORD : in STD_LOGIC_VECTOR (7 downto 0);
	C : in STD_LOGIC_VECTOR (1 to 8);
	B : in STD_LOGIC_VECTOR (1 to 8);
	SEL : in STD_LOGIC_VECTOR (1 downto 0);
	X : out STD_LOGIC_VECTOR (1 to 8);
	G1 : in STD_LOGIC;
	G2A_L : in STD_LOGIC;
	G2B_L : in STD_LOGIC;
	AEQB : out STD_LOGIC;
	BEQC : out STD_LOGIC;
	AEQC : out STD_LOGIC;
	ABCEQ : out STD_LOGIC;
	EO : out STD_LOGIC;
	GS : out STD_LOGIC;
	EI : in STD_LOGIC;
	G_L : in STD_LOGIC
); end CHAPTER5;

architecture SCHEMATIC of CHAPTER5 is

--COMPONENTS

component Z74X138H port (
	A : in STD_LOGIC;
	B : in STD_LOGIC;
	C : in STD_LOGIC;
	Y7 : out STD_LOGIC;
	G1 : in STD_LOGIC;
	G2A : in STD_LOGIC;
	G2B : in STD_LOGIC;
	Y0 : out STD_LOGIC;
	Y1 : out STD_LOGIC;
	Y2 : out STD_LOGIC;
	Y3 : out STD_LOGIC;
	Y4 : out STD_LOGIC;
	Y5 : out STD_LOGIC;
	Y6 : out STD_LOGIC
); end component;

component Z74X138 port (
	A : in STD_LOGIC;
	B : in STD_LOGIC;
	C : in STD_LOGIC;
	G1 : in STD_LOGIC;
	G2A : in STD_LOGIC;
	G2B : in STD_LOGIC;
	Y0 : out STD_LOGIC;
	Y1 : out STD_LOGIC;
	Y2 : out STD_LOGIC;
	Y3 : out STD_LOGIC;
	Y4 : out STD_LOGIC;
	Y5 : out STD_LOGIC;
	Y6 : out STD_LOGIC;
	Y7 : out STD_LOGIC
); end component;

component Z74X138P port (
	A : in STD_LOGIC;
	B : in STD_LOGIC;
	C : in STD_LOGIC;
	EN1 : in STD_LOGIC;
	EN2 : in STD_LOGIC;
	G1 : in STD_LOGIC;
	G2A : in STD_LOGIC;
	G2B : in STD_LOGIC;
	POL : in STD_LOGIC;
	Y0 : out STD_LOGIC;
	Y1 : out STD_LOGIC;
	Y2 : out STD_LOGIC;
	Y3 : out STD_LOGIC;
	Y4 : out STD_LOGIC;
	Y5 : out STD_LOGIC;
	Y6 : out STD_LOGIC;
	Y7 : out STD_LOGIC
); end component;

component EQUALCHK port (
	A : in STD_LOGIC_VECTOR (0 to 7);
	C : in STD_LOGIC_VECTOR (0 to 7);
	B : in STD_LOGIC_VECTOR (0 to 7);
	AEQB : inout STD_LOGIC;
	AEQC : inout STD_LOGIC;
	ABCEQ : out STD_LOGIC;
	BEQC : inout STD_LOGIC
); end component;

component INV8 port (
	I : in STD_LOGIC_VECTOR (7 downto 0);
	O : out STD_LOGIC_VECTOR (7 downto 0)
); end component;

component V74X138 port (
	Y_L : out STD_LOGIC_VECTOR (0 to 7);
	A : in STD_LOGIC_VECTOR (2 downto 0);
	G1 : in STD_LOGIC;
	G2A_L : in STD_LOGIC;
	G2B_L : in STD_LOGIC
); end component;

component V74X138 port (
	Y_L : out STD_LOGIC_VECTOR (0 to 7);
	A : in STD_LOGIC_VECTOR (2 downto 0);
	G1 : in STD_LOGIC;
	G2A_L : in STD_LOGIC;
	G2B_L : in STD_LOGIC
); end component;

component V74X138 port (
	Y_L : out STD_LOGIC_VECTOR (0 to 7);
	A : in STD_LOGIC_VECTOR (2 downto 0);
	G1 : in STD_LOGIC;
	G2B_L : in STD_LOGIC;
	G2A_L : in STD_LOGIC
); end component;

component V74X138 port (
	Y_L : out STD_LOGIC_VECTOR (0 to 7);
	A : in STD_LOGIC_VECTOR (2 downto 0);
	G2A_L : in STD_LOGIC;
	G2B_L : in STD_LOGIC;
	G1 : in STD_LOGIC
); end component;

component V74X138 port (
	Y_L : out STD_LOGIC_VECTOR (0 to 7);
	A : in STD_LOGIC_VECTOR (2 downto 0);
	G1 : in STD_LOGIC;
	G2A_L : in STD_LOGIC;
	G2B_L : in STD_LOGIC
); end component;

component V74X148 port (
	I : in STD_LOGIC_VECTOR (7 downto 0);
	A : out STD_LOGIC_VECTOR (2 downto 0);
	EO : out STD_LOGIC;
	EI : in STD_LOGIC;
	GS : out STD_LOGIC
); end component;

component V3STATEX port (
	X : out STD_LOGIC_VECTOR (1 to 8);
	C : in STD_LOGIC_VECTOR (1 to 8);
	B : in STD_LOGIC_VECTOR (1 to 8);
	A : in STD_LOGIC_VECTOR (1 to 8);
	SEL : in STD_LOGIC_VECTOR (1 downto 0);
	G_L : in STD_LOGIC
); end component;

--SIGNALS

signal YB_L0_ASSIGN_B0 : STD_LOGIC;
signal YB_L1_ASSIGN_B1 : STD_LOGIC;
signal YB_L2_ASSIGN_B2 : STD_LOGIC;
signal YB_L3_ASSIGN_B3 : STD_LOGIC;
signal YB_L4_ASSIGN_B4 : STD_LOGIC;
signal YB_L5_ASSIGN_B5 : STD_LOGIC;
signal YB_L6_ASSIGN_B6 : STD_LOGIC;
signal YB_L7_ASSIGN_B7 : STD_LOGIC;
signal YC_L0_ASSIGN_C0 : STD_LOGIC;
signal YC_L1_ASSIGN_C1 : STD_LOGIC;
signal YC_L2_ASSIGN_C2 : STD_LOGIC;
signal YC_L3_ASSIGN_C3 : STD_LOGIC;
signal YC_L4_ASSIGN_C4 : STD_LOGIC;
signal YC_L5_ASSIGN_C5 : STD_LOGIC;
signal YC_L6_ASSIGN_C6 : STD_LOGIC;
signal YC_L7_ASSIGN_C7 : STD_LOGIC;
signal YA_L0_ASSIGN_A0 : STD_LOGIC;
signal YA_L1_ASSIGN_A1 : STD_LOGIC;
signal YA_L2_ASSIGN_A2 : STD_LOGIC;
signal YA_L3_ASSIGN_A3 : STD_LOGIC;
signal YA_L4_ASSIGN_A4 : STD_LOGIC;
signal YA_L5_ASSIGN_A5 : STD_LOGIC;
signal YA_L6_ASSIGN_A6 : STD_LOGIC;
signal YA_L7_ASSIGN_A7 : STD_LOGIC;
signal AEQB_ASSIGN_AEQB : STD_LOGIC;
signal BEQC_ASSIGN_BEQC : STD_LOGIC;
signal AEQC_ASSIGN_AEQC : STD_LOGIC;

signal YB : STD_LOGIC_VECTOR (7 downto 0);
signal YC : STD_LOGIC_VECTOR (7 downto 0);


begin

--SIGNAL ASSIGNMENTS

YB_L(0) <= YB_L0_ASSIGN_B0;
YB_L(1) <= YB_L1_ASSIGN_B1;
YB_L(2) <= YB_L2_ASSIGN_B2;
YB_L(3) <= YB_L3_ASSIGN_B3;
YB_L(4) <= YB_L4_ASSIGN_B4;
YB_L(5) <= YB_L5_ASSIGN_B5;
YB_L(6) <= YB_L6_ASSIGN_B6;
YB_L(7) <= YB_L7_ASSIGN_B7;
YC_L(0) <= YC_L0_ASSIGN_C0;
YC_L(1) <= YC_L1_ASSIGN_C1;
YC_L(2) <= YC_L2_ASSIGN_C2;
YC_L(3) <= YC_L3_ASSIGN_C3;
YC_L(4) <= YC_L4_ASSIGN_C4;
YC_L(5) <= YC_L5_ASSIGN_C5;
YC_L(6) <= YC_L6_ASSIGN_C6;
YC_L(7) <= YC_L7_ASSIGN_C7;
YA_L(0) <= YA_L0_ASSIGN_A0;
YA_L(1) <= YA_L1_ASSIGN_A1;
YA_L(2) <= YA_L2_ASSIGN_A2;
YA_L(3) <= YA_L3_ASSIGN_A3;
YA_L(4) <= YA_L4_ASSIGN_A4;
YA_L(5) <= YA_L5_ASSIGN_A5;
YA_L(6) <= YA_L6_ASSIGN_A6;
YA_L(7) <= YA_L7_ASSIGN_A7;
AEQB <= AEQB_ASSIGN_AEQB;
BEQC <= BEQC_ASSIGN_BEQC;
AEQC <= AEQC_ASSIGN_AEQC;

--COMPONENT INSTANCES

U14 : Z74X138H port map(
	A => A(0),
	B => A(1),
	C => A(2),
	Y7 => YB(7),
	G1 => G1,
	G2A => G2A_L,
	G2B => G2B_L,
	Y0 => YB(0),
	Y1 => YB(1),
	Y2 => YB(2),
	Y3 => YB(3),
	Y4 => YB(4),
	Y5 => YB(5),
	Y6 => YB(6)
);
U1 : Z74X138 port map(
	A => A(0),
	B => A(1),
	C => A(2),
	G1 => G1,
	G2A => G2A_L,
	G2B => G2B_L,
	Y0 => YA_L0_ASSIGN_A0,
	Y1 => YA_L1_ASSIGN_A1,
	Y2 => YA_L2_ASSIGN_A2,
	Y3 => YA_L3_ASSIGN_A3,
	Y4 => YA_L4_ASSIGN_A4,
	Y5 => YA_L5_ASSIGN_A5,
	Y6 => YA_L6_ASSIGN_A6,
	Y7 => YA_L7_ASSIGN_A7
);
U15 : Z74X138P port map(
	A => A(0),
	B => A(1),
	C => A(2),
	EN1 => G1,
	EN2 => G1,
	G1 => G1,
	G2A => G2A_L,
	G2B => G2B_L,
	POL => G1,
	Y0 => YC(0),
	Y1 => YC(1),
	Y2 => YC(2),
	Y3 => YC(3),
	Y4 => YC(4),
	Y5 => YC(5),
	Y6 => YC(6),
	Y7 => YC(7)
);
U7 : EQUALCHK port map(
	A(0) => YA_L0_ASSIGN_A0,
	A(1) => YA_L1_ASSIGN_A1,
	A(2) => YA_L2_ASSIGN_A2,
	A(3) => YA_L3_ASSIGN_A3,
	A(4) => YA_L4_ASSIGN_A4,
	A(5) => YA_L5_ASSIGN_A5,
	A(6) => YA_L6_ASSIGN_A6,
	A(7) => YA_L7_ASSIGN_A7,
	C(0) => YC_L0_ASSIGN_C0,
	C(1) => YC_L1_ASSIGN_C1,
	C(2) => YC_L2_ASSIGN_C2,
	C(3) => YC_L3_ASSIGN_C3,
	C(4) => YC_L4_ASSIGN_C4,
	C(5) => YC_L5_ASSIGN_C5,
	C(6) => YC_L6_ASSIGN_C6,
	C(7) => YC_L7_ASSIGN_C7,
	B(0) => YB_L0_ASSIGN_B0,
	B(1) => YB_L1_ASSIGN_B1,
	B(2) => YB_L2_ASSIGN_B2,
	B(3) => YB_L3_ASSIGN_B3,
	B(4) => YB_L4_ASSIGN_B4,
	B(5) => YB_L5_ASSIGN_B5,
	B(6) => YB_L6_ASSIGN_B6,
	B(7) => YB_L7_ASSIGN_B7,
	AEQB => AEQB_ASSIGN_AEQB,
	AEQC => AEQC_ASSIGN_AEQC,
	ABCEQ => ABCEQ,
	BEQC => BEQC_ASSIGN_BEQC
);
X36_I1 : INV8 port map(
	I(7) => YB(0),
	I(6) => YB(1),
	I(5) => YB(2),
	I(4) => YB(3),
	I(3) => YB(4),
	I(2) => YB(5),
	I(1) => YB(6),
	I(0) => YB(7),
	O(7) => YB_L0_ASSIGN_B0,
	O(6) => YB_L1_ASSIGN_B1,
	O(5) => YB_L2_ASSIGN_B2,
	O(4) => YB_L3_ASSIGN_B3,
	O(3) => YB_L4_ASSIGN_B4,
	O(2) => YB_L5_ASSIGN_B5,
	O(1) => YB_L6_ASSIGN_B6,
	O(0) => YB_L7_ASSIGN_B7
);
X36_I2 : INV8 port map(
	I(7) => YC(0),
	I(6) => YC(1),
	I(5) => YC(2),
	I(4) => YC(3),
	I(3) => YC(4),
	I(2) => YC(5),
	I(1) => YC(6),
	I(0) => YC(7),
	O(7) => YC_L0_ASSIGN_C0,
	O(6) => YC_L1_ASSIGN_C1,
	O(5) => YC_L2_ASSIGN_C2,
	O(4) => YC_L3_ASSIGN_C3,
	O(3) => YC_L4_ASSIGN_C4,
	O(2) => YC_L5_ASSIGN_C5,
	O(1) => YC_L6_ASSIGN_C6,
	O(0) => YC_L7_ASSIGN_C7
);
U4 : V74X138 port map(
	Y_L(0) => YB_L0_ASSIGN_B0,
	Y_L(1) => YB_L1_ASSIGN_B1,
	Y_L(2) => YB_L2_ASSIGN_B2,
	Y_L(3) => YB_L3_ASSIGN_B3,
	Y_L(4) => YB_L4_ASSIGN_B4,
	Y_L(5) => YB_L5_ASSIGN_B5,
	Y_L(6) => YB_L6_ASSIGN_B6,
	Y_L(7) => YB_L7_ASSIGN_B7,
	A(2) => A(2),
	A(1) => A(1),
	A(0) => A(0),
	G1 => G1,
	G2A_L => G2A_L,
	G2B_L => G2B_L
);
U5 : V74X138 port map(
	Y_L(0) => YA_L0_ASSIGN_A0,
	Y_L(1) => YA_L1_ASSIGN_A1,
	Y_L(2) => YA_L2_ASSIGN_A2,
	Y_L(3) => YA_L3_ASSIGN_A3,
	Y_L(4) => YA_L4_ASSIGN_A4,
	Y_L(5) => YA_L5_ASSIGN_A5,
	Y_L(6) => YA_L6_ASSIGN_A6,
	Y_L(7) => YA_L7_ASSIGN_A7,
	A(2) => A(2),
	A(1) => A(1),
	A(0) => A(0),
	G1 => G1,
	G2A_L => G2A_L,
	G2B_L => G2B_L
);
U6 : V74X138 port map(
	Y_L(0) => YC_L0_ASSIGN_C0,
	Y_L(1) => YC_L1_ASSIGN_C1,
	Y_L(2) => YC_L2_ASSIGN_C2,
	Y_L(3) => YC_L3_ASSIGN_C3,
	Y_L(4) => YC_L4_ASSIGN_C4,
	Y_L(5) => YC_L5_ASSIGN_C5,
	Y_L(6) => YC_L6_ASSIGN_C6,
	Y_L(7) => YC_L7_ASSIGN_C7,
	A(2) => A(2),
	A(1) => A(1),
	A(0) => A(0),
	G1 => G1,
	G2B_L => G2B_L,
	G2A_L => G2A_L
);
U8 : EQUALCHK port map(
	A(0) => YA_L0_ASSIGN_A0,
	A(1) => YA_L1_ASSIGN_A1,
	A(2) => YA_L2_ASSIGN_A2,
	A(3) => YA_L3_ASSIGN_A3,
	A(4) => YA_L4_ASSIGN_A4,
	A(5) => YA_L5_ASSIGN_A5,
	A(6) => YA_L6_ASSIGN_A6,
	A(7) => YA_L7_ASSIGN_A7,
	C(0) => YC_L0_ASSIGN_C0,
	C(1) => YC_L1_ASSIGN_C1,
	C(2) => YC_L2_ASSIGN_C2,
	C(3) => YC_L3_ASSIGN_C3,
	C(4) => YC_L4_ASSIGN_C4,
	C(5) => YC_L5_ASSIGN_C5,
	C(6) => YC_L6_ASSIGN_C6,
	C(7) => YC_L7_ASSIGN_C7,
	B(0) => YB_L0_ASSIGN_B0,
	B(1) => YB_L1_ASSIGN_B1,
	B(2) => YB_L2_ASSIGN_B2,
	B(3) => YB_L3_ASSIGN_B3,
	B(4) => YB_L4_ASSIGN_B4,
	B(5) => YB_L5_ASSIGN_B5,
	B(6) => YB_L6_ASSIGN_B6,
	B(7) => YB_L7_ASSIGN_B7,
	AEQB => AEQB_ASSIGN_AEQB,
	AEQC => AEQC_ASSIGN_AEQC,
	ABCEQ => ABCEQ,
	BEQC => BEQC_ASSIGN_BEQC
);
U10 : V74X138 port map(
	Y_L(0) => YP_L(0),
	Y_L(1) => YP_L(1),
	Y_L(2) => YP_L(2),
	Y_L(3) => YP_L(3),
	Y_L(4) => YP_L(4),
	Y_L(5) => YP_L(5),
	Y_L(6) => YP_L(6),
	Y_L(7) => YP_L(7),
	A(2) => A(2),
	A(1) => A(1),
	A(0) => A(0),
	G2A_L => G2A_L,
	G2B_L => G2B_L,
	G1 => G1
);
U12 : V74X138 port map(
	Y_L(0) => YQ_L(0),
	Y_L(1) => YQ_L(1),
	Y_L(2) => YQ_L(2),
	Y_L(3) => YQ_L(3),
	Y_L(4) => YQ_L(4),
	Y_L(5) => YQ_L(5),
	Y_L(6) => YQ_L(6),
	Y_L(7) => YQ_L(7),
	A(2) => A(2),
	A(1) => A(1),
	A(0) => A(0),
	G1 => G1,
	G2A_L => G2A_L,
	G2B_L => G2B_L
);
U16 : V74X148 port map(
	I(7) => IN_KEYWORD(7),
	I(6) => IN_KEYWORD(6),
	I(5) => IN_KEYWORD(5),
	I(4) => IN_KEYWORD(4),
	I(3) => IN_KEYWORD(3),
	I(2) => IN_KEYWORD(2),
	I(1) => IN_KEYWORD(1),
	I(0) => IN_KEYWORD(0),
	A(2) => A(2),
	A(1) => A(1),
	A(0) => A(0),
	EO => EO,
	EI => EI,
	GS => GS
);
U17 : V3STATEX port map(
	X(1) => X(1),
	X(2) => X(2),
	X(3) => X(3),
	X(4) => X(4),
	X(5) => X(5),
	X(6) => X(6),
	X(7) => X(7),
	X(8) => X(8),
	C(1) => C(1),
	C(2) => C(2),
	C(3) => C(3),
	C(4) => C(4),
	C(5) => C(5),
	C(6) => C(6),
	C(7) => C(7),
	C(8) => C(8),
	B(1) => B(1),
	B(2) => B(2),
	B(3) => B(3),
	B(4) => B(4),
	B(5) => B(5),
	B(6) => B(6),
	B(7) => B(7),
	B(8) => B(8),
	A(1) => A(1),
	A(2) => A(2),
	A(3) => A(3),
	A(4) => A(4),
	A(5) => A(5),
	A(6) => A(6),
	A(7) => A(7),
	A(8) => A(8),
	SEL(1) => SEL(1),
	SEL(0) => SEL(0),
	G_L => G_L
);

end SCHEMATIC;