"
"  File:	C:\FNDTN\ACTIVE\PROJECTS\CHAPTER8\MPYSM.abl
"  created:	03/29/99 21:47:01
"  from:	'C:\FNDTN\ACTIVE\PROJECTS\CHAPTER8\MPYSM.asf'
"  by:		fsm2hdl - version: 2.0.1.49
"
module mpysm
Title 'mpysm'

Declarations

"clocks
CLK PIN;

"input ports
MAXCNT PIN;
MPY0 PIN;
RESET PIN;
START PIN;

"output ports
CLEAR PIN;
LDHP PIN;
LDMCND PIN;
MPYS1..MPYS0 PIN;
MPYS = [MPYS1..MPYS0];
RUNC PIN;
SELSUM PIN;

"******** BINARY ENCODED state machine: Sreg0 ******
	Sreg0_0 NODE istype 'reg';
xilinx property 'save Sreg0_0';
	Sreg0_1 NODE istype 'reg';
xilinx property 'save Sreg0_1';

	Sreg0 = [Sreg0_1, Sreg0_0];

	IDLE = ^b00; 
	INIT = ^b01; 
	RUN = ^b10; 
	WAIT = ^b11; 


Equations

"diagram ACTIONS

"************* state machine: Sreg0 *************
" clock signals definitions
	Sreg0.clk = CLK;
	Sreg0.clr = RESET == 1;

State_diagram Sreg0


State IDLE:
    
     IF (START == 0) THEN 
    IDLE
     ELSE  IF (START == 1) THEN 
        INIT;


State INIT:
    
    CLEAR = 1;
    LDHP = 1;
    LDMCND = 1;
    MPYS = [1,1];
     IF (1) THEN 
    RUN;


State RUN:
    
    RUNC = 1;
    LDHP = 1;
    MPYS = [0,1];
    SELSUM = MPY0;
     IF (MAXCNT == 1) THEN 
    WAIT
     ELSE  IF (MAXCNT == 0) THEN 
        RUN;


State WAIT:
    
     IF (START == 1) THEN 
    WAIT
     ELSE  IF (START == 0) THEN 
        IDLE;

" end of state machine - Sreg0


end mpysm