library IEEE;
use IEEE.std_logic_1164.all;

entity Vggame is 
  port ( CLOCK, RESET, G1, G2, G3, G4: in  STD_LOGIC;
         L1, L2, L3, L4, ERR:          out STD_LOGIC );
end;

architecture Vggameoc_arch of Vggame is
signal Sreg: STD_LOGIC_VECTOR (1 to 5);
-- bit positions of output-coded assignment: L1, L2, L3, L4, ERR
constant S1:   STD_LOGIC_VECTOR (1 to 5) := "10000";
constant S2:   STD_LOGIC_VECTOR (1 to 5) := "01000";
constant S3:   STD_LOGIC_VECTOR (1 to 5) := "00100";
constant S4:   STD_LOGIC_VECTOR (1 to 5) := "00010";
constant SERR: STD_LOGIC_VECTOR (1 to 5) := "00001";
constant SOK:  STD_LOGIC_VECTOR (1 to 5) := "00000";
begin

  process (CLOCK)
  begin
    if CLOCK'event and CLOCK = '1' then
      if RESET = '1' then Sreg <= SOK; else
        case Sreg is
          when S1   => if    G2='1' or G3='1' or G4='1' then Sreg <= SERR;
                       elsif G1='1'                     then Sreg <= SOK;
                       else                                  Sreg <= S2;
                       end if;
          when S2   => if    G1='1' or G3='1' or G4='1' then Sreg <= SERR;
                       elsif G1='1'                     then Sreg <= SOK;
                       else                                  Sreg <= S3;
                       end if;
          when S3   => if    G1='1' or G2='1' or G4='1' then Sreg <= SERR;
                       elsif G1='1'                     then Sreg <= SOK;
                       else                                  Sreg <= S4;
                       end if;
          when S4   => if    G1='1' or G2='1' or G3='1' then Sreg <= SERR;
                       elsif G1='1'                     then Sreg <= SOK;
                       else                                  Sreg <= S1;
                       end if;
          when SOK | SERR => if G1='0' and G2='0' and G3='0' and G4='0' 
                                 then Sreg <= S1; end if;
          when others => Sreg <= S1;
        end case;
      end if;
    end if;
  end process;      

  L1  <= Sreg(1);
  L2  <= Sreg(2);
  L3  <= Sreg(3);
  L4  <= Sreg(4);
  ERR <= Sreg(5);

end Vggameoc_arch;