library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity Vonescnt is 
  port ( CLOCK, RESET, X, Y: in STD_LOGIC;
         Z: out STD_LOGIC );
end;

architecture Vonescte_arch of Vonescnt is
subtype COUNTER is UNSIGNED (1 downto 0);
signal COUNT: COUNTER;
constant ZERO: COUNTER := "00";
begin

  process (CLOCK)
  variable ONES: STD_LOGIC_VECTOR (1 to 2);
  begin
    if CLOCK'event and CLOCK = '1' then
      ONES := (X, Y);
      if RESET = '1' then COUNT <= ZERO;
      else case ONES is
             when "01" | "10" => COUNT <= COUNT + "01";
             when "11"        => COUNT <= COUNT + "10";
             when others      => null;
           end case;
      end if;
    end if;
  end process;

  Z <= '1' when COUNT = ZERO else '0';
         
end Vonescte_arch;