--
--  File: C:\FNDTN\ACTIVE\PROJECTS\CHAPTER9\foo.vhd
-- created: 06/03/99 13:51:54
--  from: 'C:\FNDTN\ACTIVE\PROJECTS\CHAPTER9\foo.asf'
--  by fsm2hdl - version: 2.0.1.49
--
library IEEE;
use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library SYNOPSYS;
use SYNOPSYS.attributes.all;

entity foo is 
  port (CLK: in STD_LOGIC;
        I: in STD_LOGIC;
        O: in STD_LOGIC);
end;

architecture foo_arch of foo is


-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is ();
signal Sreg0: Sreg0_type;

begin
--concurrent signal assignments
--diagram ACTIONS;


Sreg0_machine: process (CLK)

begin

if CLK'event and CLK = '1' then
	case Sreg0 is
		when others =>
			null;
	end case;
end if;
end process;

end foo_arch;