

=================

Chip TwoInRow_OPT

=================



Summary Information:

--------------------

Type: Optimized implementation

Source: TwoInRow, up to date

Status: 0 errors, 0 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: TwoInRow_arch

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

TwoInRow: defined in C:\fndtn\Active\projects\CHAPTER6\TwoInRow.vhd



Primitive reference count:

--------------------------

AND2         24

AND3          4

AND4          1

AND5          3

AND7          1

INV          24

OR2          14

OR3           5

OR4           3

OR5           2

OR6           2

OR7           1

OR8           2



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00       9.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

X<1><1>                 n/a        n/a     (O)                  

X<1><2>                 n/a        n/a     (O)                  

X<1><3>                 n/a        n/a     (O)                  

X<2><1>                 n/a        n/a     (O)                  

X<2><2>                 n/a        n/a     (O)                  

X<2><3>                 n/a        n/a     (O)                  

X<3><1>                 n/a        n/a     (O)                  

X<3><2>                 n/a        n/a     (O)                  

X<3><3>                 n/a        n/a     (O)                  

Y<1><1>                 n/a        n/a     (O)                  

Y<1><2>                 n/a        n/a     (O)                  

Y<1><3>                 n/a        n/a     (O)                  

Y<2><1>                 n/a        n/a     (O)                  

Y<2><2>                 n/a        n/a     (O)                  

Y<2><3>                 n/a        n/a     (O)                  

Y<3><1>                 n/a        n/a     (O)                  

Y<3><2>                 n/a        n/a     (O)                  

Y<3><3>                 n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

MOVE<3>                1.00        n/a     (I)                  

MOVE<2>                1.00        n/a     (I)                  

MOVE<1>                1.00        n/a     (I)                  

MOVE<0>                1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port         9.00       1.00       0     /TwoInRow_OPT/MOVE<3>

OR5          9.00       1.00       0     /TwoInRow_OPT/C74/O  

OR5          8.00       0.00       3     /TwoInRow_OPT/C74/I2 

INV          8.00       0.00       3     /TwoInRow_OPT/C83/O  

INV          7.00        n/a       1     /TwoInRow_OPT/C83/I  

OR6          7.00        n/a       1     /TwoInRow_OPT/C84/O  

OR6          6.00        n/a       1     /TwoInRow_OPT/C84/I5 

OR6          6.00        n/a       1     /TwoInRow_OPT/C85/O  

OR6          5.00        n/a       5     /TwoInRow_OPT/C85/I1 

INV          5.00        n/a       5     /TwoInRow_OPT/C87/O  

INV          4.00        n/a       4     /TwoInRow_OPT/C87/I  

OR3          4.00        n/a       4     /TwoInRow_OPT/C127/O 

OR3          3.00        n/a       1     /TwoInRow_OPT/C127/I2

AND2         3.00        n/a       1     /TwoInRow_OPT/C128/O 

AND2         2.00        n/a       1     /TwoInRow_OPT/C128/I0

OR2          2.00        n/a       1     /TwoInRow_OPT/C131/O 

OR2          1.00        n/a       3     /TwoInRow_OPT/C131/I0

INV          1.00        n/a       3     /TwoInRow_OPT/C132/O 

INV          0.00        n/a       6     /TwoInRow_OPT/C132/I 

port         0.00        n/a       6     /TwoInRow_OPT/X<3><1>

