library IEEE;
use IEEE.std_logic_1164.all;

entity INCR5 is
    port ( A:  in  STD_LOGIC_VECTOR(4 downto 0);
           CI: in  STD_LOGIC;
           S:  out STD_LOGIC_VECTOR(5 downto 0) );
end INCR5;

architecture INCR5_arch of INCR5 is
signal C: STD_LOGIC_VECTOR(0 to 4);
begin
  C(0) <= CI;
  U1: for i in 0 to 4 generate
    S(i) <= A(i) xor C(i);
    C(i+1) <= A(i) and C(i);
  end generate;
  S(5) <= C(5);
end INCR5_arch;
