

=================

Chip Vmodecmp_OPT

=================



Summary Information:

--------------------

Type: Optimized implementation

Source: Vmodecmp, up to date

Status: 0 errors, 0 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: Vmodecmp_arch

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

Vmodecmp: defined in C:\FNDTN\ACTIVE\PROJECTS\CHAPTER6\Vmodecmp.vhd



Primitive reference count:

--------------------------

AND2         40

AND3         10

AND4          5

AND5          7

AND6          5

AND7          6

AND8          9

INV          34

OR2          39

OR3           3

OR4           5

OR5          13

OR6          12

OR7           8

OR8           2

XOR2         32



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00      10.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

M<1>                    n/a        n/a     (O)                  

M<0>                    n/a        n/a     (O)                  

A<31>                   n/a        n/a     (O)                  

A<30>                   n/a        n/a     (O)                  

A<29>                   n/a        n/a     (O)                  

A<28>                   n/a        n/a     (O)                  

A<27>                   n/a        n/a     (O)                  

A<26>                   n/a        n/a     (O)                  

A<25>                   n/a        n/a     (O)                  

A<24>                   n/a        n/a     (O)                  

A<23>                   n/a        n/a     (O)                  

A<22>                   n/a        n/a     (O)                  

A<21>                   n/a        n/a     (O)                  

A<20>                   n/a        n/a     (O)                  

A<19>                   n/a        n/a     (O)                  

A<18>                   n/a        n/a     (O)                  

A<17>                   n/a        n/a     (O)                  

A<16>                   n/a        n/a     (O)                  

A<15>                   n/a        n/a     (O)                  

A<14>                   n/a        n/a     (O)                  

A<13>                   n/a        n/a     (O)                  

A<12>                   n/a        n/a     (O)                  

A<11>                   n/a        n/a     (O)                  

A<10>                   n/a        n/a     (O)                  

A<9>                    n/a        n/a     (O)                  

A<8>                    n/a        n/a     (O)                  

A<7>                    n/a        n/a     (O)                  

A<6>                    n/a        n/a     (O)                  

A<5>                    n/a        n/a     (O)                  

A<4>                    n/a        n/a     (O)                  

A<3>                    n/a        n/a     (O)                  

A<2>                    n/a        n/a     (O)                  

A<1>                    n/a        n/a     (O)                  

A<0>                    n/a        n/a     (O)                  

B<31>                   n/a        n/a     (O)                  

B<30>                   n/a        n/a     (O)                  

B<29>                   n/a        n/a     (O)                  

B<28>                   n/a        n/a     (O)                  

B<27>                   n/a        n/a     (O)                  

B<26>                   n/a        n/a     (O)                  

B<25>                   n/a        n/a     (O)                  

B<24>                   n/a        n/a     (O)                  

B<23>                   n/a        n/a     (O)                  

B<22>                   n/a        n/a     (O)                  

B<21>                   n/a        n/a     (O)                  

B<20>                   n/a        n/a     (O)                  

B<19>                   n/a        n/a     (O)                  

B<18>                   n/a        n/a     (O)                  

B<17>                   n/a        n/a     (O)                  

B<16>                   n/a        n/a     (O)                  

B<15>                   n/a        n/a     (O)                  

B<14>                   n/a        n/a     (O)                  

B<13>                   n/a        n/a     (O)                  

B<12>                   n/a        n/a     (O)                  

B<11>                   n/a        n/a     (O)                  

B<10>                   n/a        n/a     (O)                  

B<9>                    n/a        n/a     (O)                  

B<8>                    n/a        n/a     (O)                  

B<7>                    n/a        n/a     (O)                  

B<6>                    n/a        n/a     (O)                  

B<5>                    n/a        n/a     (O)                  

B<4>                    n/a        n/a     (O)                  

B<3>                    n/a        n/a     (O)                  

B<2>                    n/a        n/a     (O)                  

B<1>                    n/a        n/a     (O)                  

B<0>                    n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

EQ                     1.00        n/a     (I)                  

GT                     1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port        10.00       1.00       0     /Vmodecmp_OPT/GT     

OR2         10.00       1.00       0     /Vmodecmp_OPT/C83/O  

OR2          9.00       0.00       1     /Vmodecmp_OPT/C83/I1 

AND2         9.00       0.00       1     /Vmodecmp_OPT/C84/O  

AND2         8.00        n/a       1     /Vmodecmp_OPT/C84/I0 

OR7          8.00        n/a       1     /Vmodecmp_OPT/C86/O  

OR7          7.00        n/a       1     /Vmodecmp_OPT/C86/I4 

AND7         7.00        n/a       1     /Vmodecmp_OPT/C132/O 

AND7         6.00        n/a       1     /Vmodecmp_OPT/C132/I4

OR6          6.00        n/a       1     /Vmodecmp_OPT/C160/O 

OR6          5.00        n/a       1     /Vmodecmp_OPT/C160/I0

AND7         5.00        n/a       1     /Vmodecmp_OPT/C179/O 

AND7         4.00        n/a       1     /Vmodecmp_OPT/C179/I5

OR4          4.00        n/a       1     /Vmodecmp_OPT/C181/O 

OR4          3.00        n/a       1     /Vmodecmp_OPT/C181/I0

AND4         3.00        n/a       1     /Vmodecmp_OPT/C185/O 

AND4         2.00        n/a       2     /Vmodecmp_OPT/C185/I1

OR2          2.00        n/a       2     /Vmodecmp_OPT/C187/O 

OR2          1.00        n/a       4     /Vmodecmp_OPT/C187/I1

INV          1.00        n/a       4     /Vmodecmp_OPT/C298/O 

INV          0.00        n/a       1     /Vmodecmp_OPT/C298/I 

port         0.00        n/a       1     /Vmodecmp_OPT/B<2>   

