

==============

Chip fixup_OPT

==============



Summary Information:

--------------------

Type: Optimized implementation

Source: fixup, up to date

Status: 0 errors, 0 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: fixup_arch

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

fixup: defined in C:\fndtn\Active\projects\CHAPTER6\fixup.vhd



Primitive reference count:

--------------------------

AND2         27

AND3         11

BUF           1

INV          21

OR2          30

OR3          12



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00       8.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

DIN<15>                0.00       0.00     (O)                  

DIN<14>                 n/a        n/a     (O)                  

DIN<13>                 n/a        n/a     (O)                  

DIN<12>                 n/a        n/a     (O)                  

DIN<11>                 n/a        n/a     (O)                  

DIN<10>                 n/a        n/a     (O)                  

DIN<9>                  n/a        n/a     (O)                  

DIN<8>                  n/a        n/a     (O)                  

DIN<7>                  n/a        n/a     (O)                  

DIN<6>                  n/a        n/a     (O)                  

DIN<5>                  n/a        n/a     (O)                  

DIN<4>                  n/a        n/a     (O)                  

DIN<3>                  n/a        n/a     (O)                  

DIN<2>                  n/a        n/a     (O)                  

DIN<1>                  n/a        n/a     (O)                  

DIN<0>                  n/a        n/a     (O)                  

S<3>                    n/a        n/a     (O)                  

S<2>                    n/a        n/a     (O)                  

S<1>                    n/a        n/a     (O)                  

S<0>                    n/a        n/a     (O)                  

FEN                     n/a        n/a     (O)                  

FDAT                    n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

DOUT<15>               1.00       0.00     (I)                  

DOUT<14>               1.00        n/a     (I)                  

DOUT<13>               1.00        n/a     (I)                  

DOUT<12>               1.00        n/a     (I)                  

DOUT<11>               1.00        n/a     (I)                  

DOUT<10>               1.00        n/a     (I)                  

DOUT<9>                1.00        n/a     (I)                  

DOUT<8>                1.00        n/a     (I)                  

DOUT<7>                1.00        n/a     (I)                  

DOUT<6>                1.00        n/a     (I)                  

DOUT<5>                1.00        n/a     (I)                  

DOUT<4>                1.00        n/a     (I)                  

DOUT<3>                1.00        n/a     (I)                  

DOUT<2>                1.00        n/a     (I)                  

DOUT<1>                1.00        n/a     (I)                  

DOUT<0>                1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port         8.00       1.00       0     /fixup_OPT/DOUT<9>   

INV          8.00       1.00       0     /fixup_OPT/C221/O    

INV          7.00       0.00       1     /fixup_OPT/C221/I    

OR2          7.00       0.00       1     /fixup_OPT/C222/O    

OR2          6.00        n/a       1     /fixup_OPT/C222/I0   

AND2         6.00        n/a       1     /fixup_OPT/C224/O    

AND2         5.00        n/a       2     /fixup_OPT/C224/I0   

INV          5.00        n/a       2     /fixup_OPT/C229/O    

INV          4.00        n/a       4     /fixup_OPT/C229/I    

AND2         4.00        n/a       4     /fixup_OPT/C230/O    

AND2         3.00        n/a       3     /fixup_OPT/C230/I0   

INV          3.00        n/a       3     /fixup_OPT/C236/O    

INV          2.00        n/a       8     /fixup_OPT/C236/I    

OR2          2.00        n/a       8     /fixup_OPT/C237/O    

OR2          1.00        n/a       5     /fixup_OPT/C237/I0   

INV          1.00        n/a       5     /fixup_OPT/C262/O    

INV          0.00        n/a       2     /fixup_OPT/C262/I    

port         0.00        n/a       2     /fixup_OPT/S<3>      

