

=================

Chip Vcnt1str_OPT

=================



Summary Information:

--------------------

Type: Optimized implementation

Source: Vcnt1str, up to date

Status: 0 errors, 0 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: Vcnt1str_arch

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

Vcnt1str: defined in C:\fndtn\Active\projects\CHAPTER6\Vcnt1str.vhd



Primitive reference count:

--------------------------

AND2         71

AND3          1

INV           6

OR2          18

OR3          19

XOR2          5

XOR3         26



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00      12.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

D<31>                   n/a        n/a     (O)                  

D<30>                   n/a        n/a     (O)                  

D<29>                   n/a        n/a     (O)                  

D<28>                   n/a        n/a     (O)                  

D<27>                   n/a        n/a     (O)                  

D<26>                   n/a        n/a     (O)                  

D<25>                   n/a        n/a     (O)                  

D<24>                   n/a        n/a     (O)                  

D<23>                   n/a        n/a     (O)                  

D<22>                   n/a        n/a     (O)                  

D<21>                   n/a        n/a     (O)                  

D<20>                   n/a        n/a     (O)                  

D<19>                   n/a        n/a     (O)                  

D<18>                   n/a        n/a     (O)                  

D<17>                   n/a        n/a     (O)                  

D<16>                   n/a        n/a     (O)                  

D<15>                   n/a        n/a     (O)                  

D<14>                   n/a        n/a     (O)                  

D<13>                   n/a        n/a     (O)                  

D<12>                   n/a        n/a     (O)                  

D<11>                   n/a        n/a     (O)                  

D<10>                   n/a        n/a     (O)                  

D<9>                    n/a        n/a     (O)                  

D<8>                    n/a        n/a     (O)                  

D<7>                    n/a        n/a     (O)                  

D<6>                    n/a        n/a     (O)                  

D<5>                    n/a        n/a     (O)                  

D<4>                    n/a        n/a     (O)                  

D<3>                    n/a        n/a     (O)                  

D<2>                    n/a        n/a     (O)                  

D<1>                    n/a        n/a     (O)                  

D<0>                    n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

SUM<5>                 1.00        n/a     (I)                  

SUM<4>                 1.00        n/a     (I)                  

SUM<3>                 1.00        n/a     (I)                  

SUM<2>                 1.00        n/a     (I)                  

SUM<1>                 1.00        n/a     (I)                  

SUM<0>                 1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port        12.00       1.00       0     /Vcnt1str_OPT/SUM<5> 

AND2        12.00       1.00       0     /Vcnt1str_OPT/C9/O   

AND2        11.00       0.00       2     /Vcnt1str_OPT/C9/I0  

AND3        11.00       0.00       2     /Vcnt1str_OPT/C14/O  

AND3        10.00        n/a       2     /Vcnt1str_OPT/C14/I2 

XOR3        10.00        n/a       2     /Vcnt1str_OPT/C15/O  

XOR3         9.00        n/a       3     /Vcnt1str_OPT/C15/I2 

OR3          9.00        n/a       3     /Vcnt1str_OPT/C16/O  

OR3          8.00        n/a       1     /Vcnt1str_OPT/C16/I0 

AND2         8.00        n/a       1     /Vcnt1str_OPT/C19/O  

AND2         7.00        n/a       3     /Vcnt1str_OPT/C19/I0 

OR3          7.00        n/a       3     /Vcnt1str_OPT/C55/O  

OR3          6.00        n/a       1     /Vcnt1str_OPT/C55/I0 

AND2         6.00        n/a       1     /Vcnt1str_OPT/C58/O  

AND2         5.00        n/a       3     /Vcnt1str_OPT/C58/I0 

XOR3         5.00        n/a       3     /Vcnt1str_OPT/C94/O  

XOR3         4.00        n/a       3     /Vcnt1str_OPT/C94/I0 

OR3          4.00        n/a       3     /Vcnt1str_OPT/C121/O 

OR3          3.00        n/a       1     /Vcnt1str_OPT/C121/I0

AND2         3.00        n/a       1     /Vcnt1str_OPT/C124/O 

AND2         2.00        n/a       3     /Vcnt1str_OPT/C124/I0

XOR3         2.00        n/a       3     /Vcnt1str_OPT/C140/O 

XOR3         1.00        n/a       3     /Vcnt1str_OPT/C140/I1

XOR3         1.00        n/a       3     /Vcnt1str_OPT/C142/O 

XOR3         0.00        n/a       2     /Vcnt1str_OPT/C142/I0

port         0.00        n/a       2     /Vcnt1str_OPT/D<6>   

