library IEEE;
use IEEE.std_logic_1164.all;

entity FA is
    port (
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        CI: in STD_LOGIC;
        S: out STD_LOGIC;
        CO: out STD_LOGIC
    );
end FA;

architecture FA_arch of FA is
begin
  -- <<enter your statements here>>
end FA_arch;
