

=================

Chip Vprior2i_OPT

=================



Summary Information:

--------------------

Type: Optimized implementation

Source: Vprior2i, up to date

Status: 0 errors, 0 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: Vprior2i_arch

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

Vprior2i: defined in C:\fndtn\Active\projects\CHAPTER6\Vprior2i.vhd



Primitive reference count:

--------------------------

AND2         11

AND3          3

AND4          4

AND6          2

INV          19

OR2          10

OR3           5

OR4           2

OR5           2

OR6           1

OR7           2



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00      10.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

R<0>                    n/a        n/a     (O)                  

R<1>                    n/a        n/a     (O)                  

R<2>                    n/a        n/a     (O)                  

R<3>                    n/a        n/a     (O)                  

R<4>                    n/a        n/a     (O)                  

R<5>                    n/a        n/a     (O)                  

R<6>                    n/a        n/a     (O)                  

R<7>                    n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

A<2>                   1.00        n/a     (I)                  

A<1>                   1.00        n/a     (I)                  

A<0>                   1.00        n/a     (I)                  

B<2>                   1.00        n/a     (I)                  

B<1>                   1.00        n/a     (I)                  

B<0>                   1.00        n/a     (I)                  

AVALID                 1.00        n/a     (I)                  

BVALID                 1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port        10.00       1.00       0     /Vprior2i_OPT/B<2>   

INV         10.00       1.00       0     /Vprior2i_OPT/C154/O 

INV          9.00       0.00       1     /Vprior2i_OPT/C154/I 

OR2          9.00       0.00       1     /Vprior2i_OPT/C155/O 

OR2          8.00        n/a       1     /Vprior2i_OPT/C155/I0

AND4         8.00        n/a       1     /Vprior2i_OPT/C158/O 

AND4         7.00        n/a       3     /Vprior2i_OPT/C158/I0

OR7          7.00        n/a       3     /Vprior2i_OPT/C163/O 

OR7          6.00        n/a       4     /Vprior2i_OPT/C163/I1

INV          6.00        n/a       4     /Vprior2i_OPT/C175/O 

INV          5.00        n/a       1     /Vprior2i_OPT/C175/I 

OR2          5.00        n/a       1     /Vprior2i_OPT/C176/O 

OR2          4.00        n/a       2     /Vprior2i_OPT/C176/I0

AND2         4.00        n/a       2     /Vprior2i_OPT/C191/O 

AND2         3.00        n/a       3     /Vprior2i_OPT/C191/I0

OR3          3.00        n/a       3     /Vprior2i_OPT/C193/O 

OR3          2.00        n/a       2     /Vprior2i_OPT/C193/I0

AND6         2.00        n/a       2     /Vprior2i_OPT/C197/O 

AND6         1.00        n/a       5     /Vprior2i_OPT/C197/I0

INV          1.00        n/a       5     /Vprior2i_OPT/C202/O 

INV          0.00        n/a       4     /Vprior2i_OPT/C202/I 

port         0.00        n/a       4     /Vprior2i_OPT/R<1>   

