

==============

Chip fpenc_OPT

==============



Summary Information:

--------------------

Type: Optimized implementation

Source: fpenc, up to date

Status: 0 errors, 7 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: fpenc_arch

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

fpenc: defined in C:\FNDTN\ACTIVE\PROJECTS\CHAPTER6\fpenc.vhd



Primitive reference count:

--------------------------

AND2          9

AND3          7

AND4          1

AND5          6

AND6          2

AND7          1

AND8          3

INV           8

OR2           3

OR4           2

OR7           1

OR8           4



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00       7.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

B<10>                   n/a        n/a     (O)                  

B<9>                    n/a        n/a     (O)                  

B<8>                    n/a        n/a     (O)                  

B<7>                    n/a        n/a     (O)                  

B<6>                    n/a        n/a     (O)                  

B<5>                    n/a        n/a     (O)                  

B<4>                    n/a        n/a     (O)                  

B<3>                    n/a        n/a     (O)                  

B<2>                    n/a        n/a     (O)                  

B<1>                    n/a        n/a     (O)                  

B<0>                    n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

M<3>                   1.00       0.00     (I)                  

M<2>                   1.00        n/a     (I)                  

M<1>                   1.00        n/a     (I)                  

M<0>                   1.00        n/a     (I)                  

E<2>                   1.00       0.00     (I)                  

E<1>                   1.00        n/a     (I)                  

E<0>                   1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port         7.00       1.00       0     /fpenc_OPT/E<0>      

AND2         7.00       1.00       0     /fpenc_OPT/C256/O    

AND2         6.00       0.00       1     /fpenc_OPT/C256/I0   

OR2          6.00       0.00       1     /fpenc_OPT/C257/O    

OR2          5.00        n/a       1     /fpenc_OPT/C257/I1   

AND2         5.00        n/a       1     /fpenc_OPT/C258/O    

AND2         4.00        n/a       1     /fpenc_OPT/C258/I0   

INV          4.00        n/a       1     /fpenc_OPT/C259/O    

INV          3.00        n/a       1     /fpenc_OPT/C259/I    

AND3         3.00        n/a       1     /fpenc_OPT/C260/O    

AND3         2.00        n/a       1     /fpenc_OPT/C260/I2   

OR2          2.00        n/a       1     /fpenc_OPT/C261/O    

OR2          1.00        n/a       6     /fpenc_OPT/C261/I0   

INV          1.00        n/a       6     /fpenc_OPT/C298/O    

INV          0.00        n/a      10     /fpenc_OPT/C298/I    

port         0.00        n/a      10     /fpenc_OPT/B<6>      

