

=================

Chip fixupsel_OPT

=================



Summary Information:

--------------------

Type: Optimized implementation

Source: fixupsel, up to date

Status: 0 errors, 0 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: fixupsel_struc

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

fixupsel: defined in C:\fndtn\Active\projects\CHAPTER6\fixupstr.vhd



Primitive reference count:

--------------------------

AND2         10

AND3          1

BUF           1

OR2           7

OR3           4



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00       5.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

S<3>                    n/a        n/a     (O)                  

S<2>                    n/a        n/a     (O)                  

S<1>                    n/a        n/a     (O)                  

S<0>                    n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

FSEL<15>                n/a        n/a     (I)                  

FSEL<14>               1.00        n/a     (I)                  

FSEL<13>               1.00        n/a     (I)                  

FSEL<12>               1.00        n/a     (I)                  

FSEL<11>               1.00       0.00     (I)                  

FSEL<10>               1.00        n/a     (I)                  

FSEL<9>                1.00        n/a     (I)                  

FSEL<8>                1.00        n/a     (I)                  

FSEL<7>                1.00       0.00     (I)                  

FSEL<6>                1.00        n/a     (I)                  

FSEL<5>                1.00        n/a     (I)                  

FSEL<4>                1.00        n/a     (I)                  

FSEL<3>                1.00        n/a     (I)                  

FSEL<2>                1.00        n/a     (I)                  

FSEL<1>                1.00        n/a     (I)                  

FSEL<0>                1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port         5.00       1.00       0     /fixupsel_OPT/FSEL<3>

OR2          5.00       1.00       0     /fixupsel_OPT/C397/O 

OR2          4.00       0.00       1     /fixupsel_OPT/C397/I0

OR3          4.00       0.00       1     /fixupsel_OPT/C398/O 

OR3          3.00        n/a       3     /fixupsel_OPT/C398/I2

OR2          3.00        n/a       3     /fixupsel_OPT/C402/O 

OR2          2.00        n/a       1     /fixupsel_OPT/C402/I0

AND2         2.00        n/a       1     /fixupsel_OPT/C403/O 

AND2         1.00        n/a       4     /fixupsel_OPT/C403/I0

AND2         1.00        n/a       4     /fixupsel_OPT/C414/O 

AND2         0.00        n/a       5     /fixupsel_OPT/C414/I0

port         0.00        n/a       5     /fixupsel_OPT/S<0>   

