

================

Chip Vprior2_OPT

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Summary Information:

--------------------

Type: Optimized implementation

Source: Vprior2, up to date

Status: 0 errors, 0 warnings, 0 messages

Export: exported after last optimization



Target Information:

-------------------

Vendor: Xilinx

Family: XC9500XL

Device: XC9500XL

Speed:  



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

VHDL arch: Vprior2_arch

Frequency: 50 MHz

Is module: Yes

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

Vprior2: defined in C:\FNDTN\ACTIVE\PROJECTS\CHAPTER6\Vprior2.vhd



Primitive reference count:

--------------------------

AND2         14

AND3          7

AND4          2

AND6          1

AND7          1

INV          21

OR2           9

OR3           5

OR4           2

OR5           2

OR7           1

OR8           1



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00       n/a     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00      12.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

R<0>                    n/a        n/a     (O)                  

R<1>                    n/a        n/a     (O)                  

R<2>                    n/a        n/a     (O)                  

R<3>                    n/a        n/a     (O)                  

R<4>                    n/a        n/a     (O)                  

R<5>                    n/a        n/a     (O)                  

R<6>                    n/a        n/a     (O)                  

R<7>                    n/a        n/a     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

A<2>                   1.00        n/a     (I)                  

A<1>                   1.00        n/a     (I)                  

A<0>                   1.00        n/a     (I)                  

B<2>                   1.00        n/a     (I)                  

B<1>                   1.00        n/a     (I)                  

B<0>                   1.00        n/a     (I)                  

AVALID                 1.00        n/a     (I)                  

BVALID                 1.00        n/a     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port        12.00       1.00       0     /Vprior2_OPT/B<2>    

OR4         12.00       1.00       0     /Vprior2_OPT/C270/O  

OR4         11.00       0.00       1     /Vprior2_OPT/C270/I0 

AND7        11.00       0.00       1     /Vprior2_OPT/C271/O  

AND7        10.00        n/a       2     /Vprior2_OPT/C271/I1 

INV         10.00        n/a       2     /Vprior2_OPT/C291/O  

INV          9.00        n/a       1     /Vprior2_OPT/C291/I  

AND2         9.00        n/a       1     /Vprior2_OPT/C292/O  

AND2         8.00        n/a       9     /Vprior2_OPT/C292/I0 

INV          8.00        n/a       9     /Vprior2_OPT/C312/O  

INV          7.00        n/a       6     /Vprior2_OPT/C312/I  

OR7          7.00        n/a       6     /Vprior2_OPT/C298/O  

OR7          6.00        n/a       2     /Vprior2_OPT/C298/I2 

AND6         6.00        n/a       2     /Vprior2_OPT/C285/O  

AND6         5.00        n/a       4     /Vprior2_OPT/C285/I0 

INV          5.00        n/a       4     /Vprior2_OPT/C297/O  

INV          4.00        n/a       4     /Vprior2_OPT/C297/I  

AND2         4.00        n/a       4     /Vprior2_OPT/C327/O  

AND2         3.00        n/a       7     /Vprior2_OPT/C327/I0 

INV          3.00        n/a       7     /Vprior2_OPT/C328/O  

INV          2.00        n/a       3     /Vprior2_OPT/C328/I  

OR8          2.00        n/a       3     /Vprior2_OPT/C314/O  

OR8          1.00        n/a       2     /Vprior2_OPT/C314/I1 

AND2         1.00        n/a       2     /Vprior2_OPT/C324/O  

AND2         0.00        n/a       3     /Vprior2_OPT/C324/I1 

port         0.00        n/a       3     /Vprior2_OPT/R<0>    

