GenerateVHDLModel=False
GenerateEdifModel=True
GenerateVerilogModel=False
GenerateVHDLInstantiation=False
GenerateVerilogInstantiation=False
GenerateNGDNetlist=True
IgnoreWarning=False
UserCancelled=True
TargetFamily=xc9500xl
CAEVendor=fndtn
BusNotation=B<I>
