library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity comp64 is
    port (
        A, B: in STD_LOGIC_VECTOR (63 downto 0);
        EQ, GT: out STD_LOGIC
    );
end comp64;

architecture comp64_arch of comp64 is
begin
process (A, B)
  begin
    EQ <= '0'; NE <= '0'; GT <= '0'; GE <= '0'; LT <= '0'; LE <= '0';
    if A = B then EQ <= '1'; else EQ <= '0'; end if;
    if A > B then GT <= '1'; else GT <= '0'; end if;
  end process;
end comp64_arch;
